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Freescale Semiconductor /MK61F15WS /DDR /CR05

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Interpret as CR05

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TWTR0RESERVED 0TRP0RESERVED 0TRTP0RESERVED0TMRD0RESERVED

Description

DDR Control Register 5

Fields

TWTR

Time Write-To-Read
RESERVED

Reserved
TRP

no description available
RESERVED

Reserved
TRTP

Time Read-To-Precharge
RESERVED

Reserved
TMRD

no description available
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data